1. Field of the Invention.
The present invention relates to semiconductor logic gate devices. In particular, the present invention is a field effect transistor (FET) type of logic gate.
2. Description of the Prior Art.
Integrated circuits which utilize CMOS logic gates offer the advantage of lower power consumption. CMOS integrated circuits, however, require a relatively large number of processing steps since both N channel and P channel FETs are required. In addition, the speed of the CMOS logic is limited by the transport properties of "slow" carriers (holes).
Another type of integrated circuit FET logic is direct coupled field effect transistor logic (DCFL), which generally offers higher speed than CMOS logic. A DCFL logic gate typically uses an enhancement mode FET which is connected in series with either a resistor or an active load (formed by a normally-on depletion mode FET). The input of the DCFL logic gate is connected to the gate of the FET and the output is connected to the drain of the FET (which is also connected to the source of the load). DCFL logic consumes more power than CMOS logic because when the input voltage is high, the FET is turned on and current flows through both the FET and the load. In addition, DCFL logic gates exhibit relatively low output voltage swing between the two stable output states.